This invention relates to an electronic circuit comprising field effect transistors (FETs).
An n-channel FET may be fabricated on a die or in a well of p-type semiconductor material by implanting an n-type dopant into source and drain regions of the FET. An n-type dopant may also be implanted, at a lower concentration, into a channel region between the source and drain regions to form a depletion (normally on) FET. Source and drain electrodes are formed in ohmic contact with the source and drain regions respectively, and a gate electrode is deposited over the channel region. In a metal-semiconductor FET, or MESFET, the gate electrode is deposited directly onto the channel region, and a rectifying junction is established between the gate electrode and the channel region, whereas in a metal-oxide-semiconductor FET, or MOSFET, the gate electrode is insulated from the channel region. The drain electrode and the source electrode are connected to positive and negative potential levels respectively. When the gate to source voltage (Vgs) exceeds a threshold level known as the pinch-off voltage (Vp), current is able to flow from the drain region to the source region through the channel region when the drain to source voltage (Vds) is sufficiently large.
A p-channel FET is similar to an n-channel FET, except that the die or well is of n-type conductivity and the implantations that are used to form the source, drain and channel (for a depletion FET) regions are of a p-type dopant.
The quiescent current (Idss) of a FET is the current that flows from drain to source when Vgs is zero and Vds is sufficiently large. FETs are classified as enhancement mode or depletion mode depending on the value of Idss: for an enhancement mode FET (E-FET) Idss is zero, and for a depletion mode FET (D-FET) Idss is positive.
FIG. 1 illustrates a simple D-FET source follower circuit which may be implemented using, for example, gallium arsenide MESFET technology. If the two transistors Q1 and Q2 are the same size, so that dss is the same for each transistor and Vgs1 (Vgs for the transistor Q1) is zero, no current is delivered to the load when Vin is zero. As Vin increases, Vgs1 also increases and current is delivered to the load. As Vgs1 increases, the output current increases until Vgs1 reaches a maximum value equal to a diode on voltage, which is about 0.7 v in the case of a GaAs device.
It can be shown that the maximum drain current that can be delivered by the transistor Q1 in the circuit shown in FIG. 1 is about four times the quiescent current of the transistor for a pinch-off voltage of about -0.6 v. Thus, the maximum load current is about three times the quiescent current, since the transistor Q2 also draws the quiescent current. Therefore, if a peak load current of 15 mA is required, corresponding to a maximum drain current of 20 mA, Idss must be at least 5 mA. It is desirable that the quiescent current be as small as possible, in order to minimize the power consumption of the circuit.
A push-pull amplifier can be constructed using two D-FETs, one of which supplies positive current to the load in response to positive signal excursions and the other of which sinks negative current from the load in response to negative signal excursions. When Vgs for one D-FET increases, Vgs for the other D-FET decreases, and vice versa.